The present invention is related to semiconductor technology, and particularly to NMOS transistors.
The minimum feature sizes of integrated circuit have been shrinking for years. The gate length of an MOS transistor has been decreased, and the source/drain regions and the source/drain extension regions are made shallower accordingly. In the current semiconductor technology, the depth of the source/drain regions of a semiconductor device can be less than 1000 Å.
In order to fabricate source/drain regions with reduced depth, the thermal budget should be reduced; that is to say, a lower heat treatment temperature and shorter heat treatment time are needed, which may lead to hot carrier injection (HCI) problems. The HCI refers to a high speed motion of carriers in the channel region (in the NMOS transistor, electrons are the majority carriers in the channel region) accelerated by a strong electric field into the gate dielectric layer, which causes the threshold voltage to drift and leads to lower current and degrades the operating frequency of an integrated circuit. The presence of such mobile carriers can drastically change device characteristics over prolonged periods. The accumulation of damage can eventually cause the circuit to fail as device parameters (e.g., threshold voltage) shift due to such damage. The useful life-time of integrated circuits is then affected by the life-time of an NMOS transistor itself.
In the conventional art, in order to reduce the HCI problem, a lightly doped drain (LDD) ion implantation process is adopted. Specifically, by reducing the dose of the LDD ion implantation and increasing the LDD implantation energy, a deeper LDD junction can be obtained and the strength of the transverse electric field can be reduced, thus, reducing the HCI problem. For example, methods for reducing HCI are disclosed in U.S. Pat. No. 7,795,101 and U.S. Pat. No. 7,875,521. Therefore, there is a need for methods and techniques to reduce HCI problems.